This application is based upon and claims the benefit of priority from each of the prior Japanese Patent Application No. 2002-156225 filed on May 29, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a scan flip-flop circuit for making an integrated circuit device to perform one of two kinds of operations of a scan test carried out as a shipping inspection and a normal operation performed in a normal mode. More particularly, the invention relates to a scan flip-flop circuit achieving higher operation speed, lower power consumption, and a simplified selector portion, an array of the scan flip-flop circuits, and an integrated circuit device having therein the array.
2. Description of Related Art
FIG. 9 shows an example of the configuration of a conventional scan flip-flop circuit. A scan flip-flop circuit 80 shown in FIG. 9 has a 2-to-1 selector 82, a master latch 83, and a slave latch 84. The 2-to-1 selector 82 has an input terminal SI for receiving a scan-in signal, an input terminal D for receiving a data signal, and an input terminal SC for receiving a scan control signal. When a normal operation is instructed by the scan control signal SC, the data signal D is passed. When a scan test is instructed, the scan-in signal SI is passed. A clock signal CLK is input to the master latch 83 and the slave latch 84. With the configuration, the scan flip-flop circuit 80 latches an output signal d_int of the 2-to-1 selector 82 and outputs it from the output terminal Q synchronously with the clock CLK. A truth table of the scan flip-flop circuit 80 is as shown in Table 1.
FIG. 10 shows a usage example of the scan flip-flop circuit 80 in an integrated circuit device. In the usage example of FIG. 10, a signal from the scan flip-flop circuit 80 to a logic circuit 90 and a signal from the scan flip-flop circuit 80 from a preceding stage to the scan flip-flop circuit 80 of the next stage are output from the same output terminal Q. Consequently, a net from the output terminal Q is branched, and one of the branches serves as the normal operation net 85 to the logic circuit 90 and the other branch serves as a scan net 86 to the input terminal SI of the scan flip-flop circuit 80 of the next stage.
FIG. 11 shows another example of the conventional scan flip-flop circuit. The different point between the scan flip-flop circuit 81 shown in FIG. 11 and the scan flip-flop circuit 80 is that an output terminal SO is provided in addition to the output terminal Q. The output terminal SO outputs the same signal as that from the output terminal Q and is used for connection to the scan flip-flop circuit of the next stage. Therefore, when the scan flip-flop circuit 81 is used, as shown in the usage example of FIG. 12, the normal operation net 85 and the scan net 86 are separated from each other.
FIG. 13 shows a structure example of the 2-to-1 selector 82 in the scan flip-flop circuit 80 or 81. The 2-to-1 selector 82 in FIG. 13 is constructed by total 10 transistors of PMOS transistors (hereinbelow, referred to as xe2x80x9cMPxe2x80x9d) 11 to 15 and NMOS transistors (hereinbelow, referred to as xe2x80x9cMNxe2x80x9d) 11 to 15. MP11 and the MN 11 are switched by the scan control signal SC and are connected in series between a power source line VDD and a grounding conductor GND. The two transistors construct an inverter for outputting an inversion signal SN of the scan control signal SC.
Between the power source line VDD and an output line d_int, MP12 and MP13 connected in series and MP14 and MP15 connected in series are provided in parallel. MP12 is switched by the signal of the input terminal D, MP13 is switched by the scan control signal SC, MP14 is switched by the signal of the input terminal SI, and MP15 is switched by the inversion signal SN. Between the output line d_int and the grounding conductor GND, MN12 and MN13 connected in series and MN14 and MN15 connected in series are provided in parallel. MN12 is switched by the signal of the input terminal D, MN13 is switched by the inversion signal SN, MN14 is switched by the signal of the input terminal SI, and MN15 is switched by the scan control signal SC. With the configuration, when the scan control signal SC is 0 (normal operation), the output signal d_int is determined by the data signal D irrespective of the signal of the input terminal SI. When the scan control signal SC is 1 (scan test), the output signal d_int is determined by the scan-in signal SI irrespective of the signal of the input terminal D.
The conventional scan flip-flop circuit, however, has the following problems. First, the circuit shown in FIGS. 9 and 10 has a problem that propagation delay time is long. For example, in the normal operation, at the time of transmitting a data signal from the output terminal Q to the logic circuit 90, the scan net 86 branched from some midpoint becomes as a wiring load. Consequently, the operation speed of the integrated circuit device is slow, and power consumption is high. In the circuit of FIGS. 11 and 12, the scan net 86 does not become a wiring load in the normal operation. However, a drive circuit is necessary for each of the output terminals Q and SO. Since the output terminal SO performs the same operation as that of the output terminal Q in the normal operation, power consumption is high.
In any of the circuit of FIGS. 9 and 10 and the circuit of FIGS. 11 and 12, as the 2-to-1 selector 82, a complicated configuration as shown in FIG. 13 has to be used. The 2-to-1 selector 82 of FIG. 13 includes three pairs of transistors switched by the scan control signal SC or the inversion signal SN of the scan control signal SC so that redundancy is high. The reason why such a complicated configuration has to be used is that a signal input to the input terminal SI is inconstant even in the normal operation (in which the scan control signal SC is 0). Therefore, to prevent the output signal d_int in the normal operation from being influenced by the signal of the input terminal SI, the complicated configuration as shown in FIG. 13 is necessary.
The present invention has been achieved to solve the problems of the conventional scan flip-flop circuits. An object of the invention is to provide a scan flip-flop circuit achieving higher operation speed, lower power consumption, and a simplified selector portion, an array of the scan flip-flop circuits, and an integrated circuit device having therein the array.
A scan flip-flop circuit of the present invention directed to achieve the object, for receiving a first signal and a second signal, passing the first signal in a first operation, and passing the second signal in a second operation, includes: a selecting section having a first input terminal for receiving the first signal, a second input terminal for receiving the second signal, and a third input terminal for receiving a control signal instructing one of the first and second operations to be performed, for outputting a signal based on the first signal when the control signal instructs the first operation and outputting a signal based on the second signal when the control signal instructs the second operation; a latch section for latching a signal based on the output signal of the selecting section synchronously with a clock and outputting the signal; a first output terminal for outputting an output signal of the latch section; and a second output terminal provided separately from the first output terminal, for outputting a fixed signal in the first operation and outputting a signal based on the second signal in the second operation.
The selecting section has a 2-1 OR-AND-INVERTER configuration which outputs inversion of AND of an input signal to the second input terminal and OR of the input signal to the first input terminal and the input signal to the third input terminal. Alternatively, the selecting section has a 2-1 AND-OR-INVERTER configuration which outputs inversion of OR of an input signal to the second input terminal and the AND of the input signal to the first input terminal and an input signal to the third input terminal. The selecting section of the OR-AND-INVERTER configuration is used in the case where the second operation is instructed by the high level of the scan control signal and the first operation is instructed by the low level of the scan control signal. In contrast, the selecting section of the AND-OR-INVERTER configuration is used in the case where the first operation is instructed by the high level of the scan control signal and the second operation is instructed by the low level of the scan control signal.
In the scan flip-flop circuit, separately from the first output terminal, a second output terminal is provided. Consequently, a wire connected to the second output terminal does not become a load in the first operation. Therefore, the first operation can be performed at high speed. In the first operation, an output of the second output terminal is fixed. With the configuration, there are the following two advantages. Firstly, low power consumption is secured at the first operation. Secondly, as the selecting section, a relatively simple configuration such as the OR-AND-INVERTER configuration or the AND-OR-INVERTER configuration can be employed.
A scan flip-flop circuit array of the invention is constructed by a plurality of scan flip-flop circuits of the invention, a signal of a second output terminal of a scan flip-flop circuit of the preceding stage is input to a second input terminal of a scan flip-flop circuit of the next stage. An integrated circuit device of the invention has a scan flip-flop circuit array and a main operation circuit for receiving a first or second signal from the scan flip-flop circuit array.
The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.